Download PDF by Guang R. Gao (auth.), Chris Jesshope, Colin Egan (eds.): Advances in Computer Systems Architecture: 11th Asia-Pacific

By Guang R. Gao (auth.), Chris Jesshope, Colin Egan (eds.)

ISBN-10: 3540400567

ISBN-13: 9783540400561

On behalf of the entire humans focused on this system choice, this system committee contributors in addition to a number of different reviewers, we're either relieved and happy to provide you with the complaints of the 2006 Asia-Pacific computers structure convention (ACSAC 2006), that is being hosted in Shanghai on September 6–8, 2006. this can be the eleventh in a chain of meetings, which began lifestyles in Australia, because the machine structure part of the Australian machine technology Week. In 1999 it ventured clear of its roots for the 1st time, and the fourth Australasian machine structure convention used to be held within the attractive urban of Sails (Auckland, New Zealand). probably it was once as a result of an absence of the other computing device structure convention in Asia or simply the appeal of touring to the Southern Hemisphere however the convention grew to become more and more foreign in the course of the next 3 years and likewise replaced its identify to incorporate desktops structure, reflecting extra the scope of the convention, which embraces either architectural and platforms matters. In 2003, the convention back ventured offshore to mirror its constituency and because then has been held in Japan within the attractive urban of Aizu-Wakamatsu, through Beijing and Singapore. This 12 months it back returns to China and subsequent yr will movement to Korea for the 1st time, the place will probably be equipped via the Korea University.

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Additional info for Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedings

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In this paper, we distinguish the wakeup prediction policy from the leakage saving circuit technique. The wakeup prediction policy predicts which cache line will be woken up, while the leakage saving circuit technique is the mechanism for putting lines to sleep and waking them up, independent of the prediction policy. al proposed a refinement of the drowsy technique, called super-drowsy cache [9]. A single-Vdd cache line voltage controller with Schmitt trigger inverter replaces multiple supply voltage sources in order to alleviate interconnect routing space.

Al. proposed the Loop policy [21] where all cache lines are put into the drowsy mode after each loop was executed. This bears some similarity to the DHS (Dynamic HotSpot Based Leakage Management) policy, which was proposed in [5]. DHS makes use of the branch target buffer (BTB), since branch behavior is an important factor in shaping the instruction access behavior. In the DHS policy, the global turn-off (drowsy) signal is issued when a new loop-based hotspot is detected. Thus this policy can lower the supply voltage of unused cache lines before the update window expires by detecting that execution will remain in a new loop-based hotspot.

131-140. 12. Y. Li, D. Parikh, Y. Zhang, K. Sankaranarayanan, M. Stan, and K. Skadron. StatePreserving vs. Non-State-Preserving Leakage Control in Caches. Proc. of the Design Automation and Test in Europe Conference. 2004, pp. 22-27. 13. S. Manne, A. Klauser, and D. Grunwald, Pipeline Gating : Speculation Control for Energy Reduction. Proc. of Int. Symp. 132-141. 14. S. McFaring. Combining Branch Predictors. Technical Note TN-36. DEC June 1993. 15. K. Nii et. al. A Low Power SRAM Using Auto-Backgate-Controlled MT-CMOS.

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Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedings by Guang R. Gao (auth.), Chris Jesshope, Colin Egan (eds.)

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